D flip-flop
That block outputs on Q its input state ( D) when the enable input ( en) is set and on the rising edge of the clock input ( clk). The !Q output is the logical negation of Q. This flip-flop is also known as a delay flip-flop because the state of the input is modified only at the next rising edge of the clock.
The D flip-flop is used as a basic cell of shift-registers.
The truth table of this block is the following:
Non-Rising where * `X`* stands for “indifferent” and * `Q n-1 `* is the previous output state of * `Q n `* .
The block supports the following types :
Inputs:
- D: scalar. Scilab’s int8 data type only.
- en: scalar. Scilab’s real double.
- clk: scalar. Scilab’s real double.
A positive input is considered as logical 1, a negative or a null input as logical 0.
Outputs : scalar. Scilab’s int8 data type.